tegra: fdt: Change load entry to 0x1080000
[chromiumos/third_party/u-boot.git] / board / nvidia / seaboard / tegra2-seaboard.dts
1 /dts-v1/;
2
3 /memreserve/ 0x1c000000 0x04000000;
4 /include/ "tegra250.dtsi"
5 /include/ "chromeos.dtsi"
6 /include/ "flashmap-twostop-2mb.dtsi"
7
8 / {
9         model = "NVIDIA Seaboard";
10         compatible = "nvidia,seaboard", "nvidia,tegra250";
11
12         config {
13                 odmdata = <0x300d8011>;
14                 hwid = "ARM SEABOARD TEST 1176";
15                 machine-arch-id = <3005>;
16
17                 /* Chrome OS specific GPIO */
18                 /*
19                  * Parameter 3 bits
20                  * bit 0: 1=output, 0=input
21                  * bit 1: 1=high, 0=low
22                  * bit 2: 1=active low, 0=active high
23                  */
24                 write-protect-switch    = <&gpio 59 0>;
25                 recovery-switch         = <&gpio 56 4>;
26                 developer-switch        = <&gpio 168 0>;
27                 /* Seaboard's lid-switch is ignored */
28                 power-switch            = <&gpio 170 4>;
29         };
30
31         aliases {
32                 console = "/serial@70006300";
33                 usb0 = "/usb@0xc5008000";
34                 usb1 = "/usb@0xc5000000";
35
36                 sdmmc0 = "/sdhci@c8000600";
37                 sdmmc1 = "/sdhci@c8000400";
38
39                 i2c0 = "/i2c@0x7000d000";
40                 i2c1 = "/i2c@0x7000c000";
41                 i2c2 = "/i2c@0x7000c400";
42                 i2c3 = "/i2c@0x7000c500";
43         };
44
45         memory {
46                 device_type = "memory";
47                 reg = <0x00000000 0x40000000>;
48         };
49
50         serial@70006300 {
51                 status = "ok";
52                 clock-frequency = <216000000>;
53         };
54
55         /*
56          * Seaboard has a switch on GPIO67 which affects this UART. Until
57          * pinmux support is added to the FDT it is not clear how to do this,
58          * so this is a stop-gap.
59          */
60         switch {
61                 compatible = "nvidia,spi-uart-switch";
62                 uart = <&uart3>;
63
64                 /* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
65                 gpios = <&gpio 67 1>; /* Port I = 8 bit = 3: 8 * 8 + 3 */
66         };
67
68         sdhci@c8000400 {
69                 status = "ok";
70                 width = <4>;    /* width of SDIO port */
71                 removable = <1>;
72                 /* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
73                 cd-gpio = <&gpio 69 0>; /* card detect, gpio PI5 */
74                 wp-gpio = <&gpio 57 0>; /* write protect, gpio PH1 */
75                 power-gpio = <&gpio 70 3>; /* power enable, gpio PI6 */
76         };
77
78         emmc: sdhci@c8000600 {
79                 status = "ok";
80                 width = <4>;    /* width of SDIO port */
81                 removable = <0>;
82         };
83
84         lcd {
85                 compatible = "nvidia,tegra2-lcd";
86                 width = <1366>;
87                 height = <768>;
88                 bits_per_pixel = <16>;
89                 pwfm = <&pwfm2>;
90                 display = <&display1>;
91                 /* frame-buffer location = top of memory - carveout - fb */
92                 frame-buffer = <0x2f680000>;
93
94                 pixel_clock = <70600000>;
95
96                 /* Timing: ref_to_sync, sync_width. back_porch, front_porch */
97                 horiz_timing = <11 58 58 58>;
98                 vert_timing = <1 4 4 4>;
99
100                 /* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
101                 backlight-enable = <&gpio 28 1>;        /* PD4 */
102                 lvds-shutdown = <&gpio 10 1>;           /* PB2 */
103                 backlight-vdd = <&gpio 176 1>;          /* PW0 */
104                 panel-vdd = <&gpio 22 1>;               /* PC6 */
105
106                 /*
107                  * Panel required timings
108                  * Timing 1: delay between panel_vdd-rise and data-rise
109                  * Timing 2: delay between data-rise and backlight_vdd-rise
110                  * Timing 3: delay between backlight_vdd and pwm-rise
111                  * Timing 4: delay between pwm-rise and backlight_en-rise
112                  */
113                 panel-timings = <4 203 17 15>;
114         };
115
116         usb@0xc5000000 {
117                 status = "ok";
118                 host-mode = <1>;
119         };
120
121         usbphy: usbphy@0 {
122                 compatible = "smsc,usb3315";
123                 status = "ok";
124         };
125
126         usb@0xc5008000 {
127                 status = "ok";
128                 utmi = <&usbphy>;
129                 host-mode = <0>;
130         };
131
132         flash@0x70008000 {
133                 compatible = "hynix,HY27UF4G2B", "nand-flash";
134                 controller = <&nand>;
135
136                 /* How many bytes for data area */
137                 page-data-bytes = <2048>;
138
139                 /* How many ECC bytes to be generated for tag bytes */
140                 tag-ecc-bytes = <4>;
141
142                 /* How many tag bytes in spare area */
143                 tag-bytes = <20>;
144
145                 /* How many ECC bytes for data area */
146                 data-ecc-bytes = <36>;
147
148                 skipped-spare-bytes = <4>;
149
150                 /*
151                  * How many bytes in spare area
152                  * spare area = skipped bytes + ECC bytes of data area
153                  * + tag bytes + ECC bytes of tag bytes
154                  */
155                 page-spare-bytes = <64>;
156
157                 /*
158                  * MAX_TRP_TREA:
159                  * non-EDO mode: value (in ns) = Max(tRP, tREA) + 6ns
160                  * EDO mode: value (in ns) = tRP timing
161                  *
162                  * Timing values: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
163                  *      TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
164                  */
165                 timing = <26 100 20 80 20 10 12 10 70>;
166         };
167
168         nand-controller@0x70008000 {
169                 status = "ok";
170                 wp-gpio = <&gpio 59 3>;         /* PH3 */
171                 width = <8>;
172         };
173 };